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1 ps8736c 12/19/05 features ? 14.318 mhz crystal input ? selectable of 100, 133, 166, 200, 266, 333, and 400 mhz cpu output frequencies ? smbus: power management control ? spread spectrum support (-0.5% down spread) ? packaging (pb-free & green available): 56-pin tssop output features ? two pairs of differential cpu clocks ? one selectable of cpu/src clock ? seven pairs of src clocks ? six pci clocks ? one 48 mhz usb clock ? one ref clock ? one 96 mhz differential clock description pi6c410m is a high-speed, low-noise clock generator designed to work with the intel mobile pci express chipset. this spread spectrum pll based clock generator reduces emi emission and supports a wide range of frequencies. jitter performance ? < 85ps cycle-to-cycle cpu 0/1 clock jitter ? < 125ps cycle-to-cycle cpu 2 clock jitter ? < 350ps cycle-to-cycle 48 mhz clock jitter ? < 500ps cycle-to-cycle pci clock jitter ? < 125ps cycle-to-cycle src clock jitter ? < 1000ps cycle-to-cycle ref clock jitter skew performance ? < 100ps output-to-output cpu 0/1 clock skew ? < 150ps output-to-output cpu 2 clock skew ? < 500ps output-to-output pci clock skew ? < 250ps output-to-output src clock skew block diagram pin confguration pi6c410m/410ma clock generator for intel pci express mobile chipset pci_2 pci_stop# cpu_stop# fs_c / test_sel ref vss_ref xtal_in xtal_out vdd_ref sda scl vss_cpu cpu_0 cpu_0# vdd_cpu cpu_1 cpu_1# iref vss_a vdd_a cpu2_itp / src7 cpu2_itp# / src7# vdd_src src_6 src_6# src_5 src_5# vss_src vdd_pci vss_pci pci_3 pci_4 pci_5 vss_pci vdd_pci pcif_0 / itp_en pcif_1 vtt_pwrgd# / pwrdwn vdd_48 usb_48/fs_a vss_48 dot_96 dot_96# fs_b / test_mode src_0 src_0# src_1 src_1# vdd_src src_2 src_2# src_3 src_3# src_4 src_4# vdd_src 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 p ll 1 c o n t r o l usb _48 / fs _a fs _b / tes t_mo de vtt_ pwrgd# / pwrdwn di v di v di v fs _c / test_se l pci_ st op # cpu_stop # xtal os c smbu s logic ref dot_96 dot 96# usb _48 / fs _a xtal_i n xtal_out sd a sc l p ll 2 /2 pc if _0 / it p_en pci [2:5] pc if [0:1 ] src [0:6 ] src [0:6 ]# cpu[0:1] c pu [0:1]# cpu2_itp / s rc7 cpu2_itp# / src7 #
2 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset pin description pin name type pin number descriptions ref output 52 3.3v 14.31818 mhz output xtal_in input 50 14.31818 mhz crystal input xtal_out output 49 14.31818 mhz crystal output cpu[0:1] & cpu[0:1]# output 40, 41, 43, 44 differential cpu outputs src[0:6] & src[0:6]# output 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33 differential serial reference clock outputs cpu2_itp / src_7 & cpu2_itp# / src_7# output 35, 36 selectable differential cpu or src clock output itp_en = 0 @ vtt_pwrgd# assertion = src itp_en = 1 @ vtt_pwrgd# assertion = cpu pcif_0 / itp_en input / output 8 33 mhz clock output / cpu2 select when high pcif_1 output 9 33 mhz clocks outputs (free running) pci[2:5] output 3, 4, 5, 56 33 mhz clocks outputs usb_48 / fs_a input / output 12 48 mhz clock output / 3.3v lvttl inputs for cpu frequency selection dot_96 & dot_96# output 14, 15 96 mhz differential clock output pci_stop# input 55 3.3v lvttl active low input for pci stop operation. (150k-ohm internal pull-up resistor) cpu_stop# input 54 3.3v lvttl active low input for cpu stop operation. (150k-ohm internal pull-up resistor) fs_b / test_mode input 16 3.3v lvttl inputs for cpu frequency selection / test mode select: 0 = hi-z, 1 = ref/n fs_c / test_sel input 53 3.3v lvttl inputs for cpu frequency selection / test mode select if pulled to 3.3v when vtt_pwrgd# is asserted low iref input 39 external resistor connection for internal current reference vtt_pwrgd# / pwrdwn input 10 3.3v lvttl level sensitive strobe used to determine to latch the fs_a, fs_b/test_mode, fs_c/test_sel and pcif0/itp_en inputs (ac - tive low) / 3.3v lvttl active high input for power down operation. sda i/o 47 smbus compatible sdata scl input 46 smbus compatible sclock vdd_pci power 1, 7 3.3v power supply for outputs vdd_48 power 11 3.3v power supply for outputs vdd_src power 21, 28, 34 3.3v power supply for outputs vdd_cpu power 42 3.3v power supply for outputs vdd_ref power 48 3.3v power supply for outputs vss_pci ground 2, 6 ground for outputs vss_48 ground 13 ground for outputs vss_src ground 29 ground for outputs vss_cpu ground 45 ground for outputs vss_ref ground 51 ground for outputs vdd_a power 37 3.3v power supply for pll vss_a ground 38 ground for pll
3 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset functionality frequency selection (1) fs_c fs_b fs_a cpu src pcif / pci ref dot_96 usb_48 1 0 1 100 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 0 1 133 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 1 1 166 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 1 0 200 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 0 0 266 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 1 0 0 333 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 1 1 0 400 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 1 1 1 reserved 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz note: 1. refer to dc electrical characteristics for fs_a, fs_b and fs_c (v ih_fs, vil_fs) threshold levels. test mode selection (2) test_mode cpu src pcif / pci ref dot_96 usb_48 1 ref/n ref/n ref/n ref ref/n ref/n 0 hi-z hi-z hi-z hi-z hi-z hi-z note: 2. test mode will occur where the smbus bit 6 of byte 6 = 1, or fs_c/test_sel is set to logic high level. pwrdwn functionality pwrdwn cpu cpu# src src# pcif / pci ref dot_96 dot_96# usb_48 0 normal normal normal normal 33 mhz 14.318 mhz normal normal 48 mhz 1 iref 2 or float float iref 2 or float float low low iref 2 or float float low pci_stop# functionality pci_stop# cpu cpu# src src# pcif / pci ref dot_96 dot_96# usb_48 1 normal normal normal normal 33 mhz 14.318 mhz normal normal 48 mhz 0 normal normal iref 6 or float low low 14.318 mhz normal normal 48 mhz cpu_stop# functionality cpu_stop# cpu cpu# src src# pcif / pci ref dot_96 dot_96# usb_48 1 normal normal normal normal 33 mhz 14.318 mhz normal normal 48 mhz 0 iref 6 or float low normal normal 33 mhz 14.318 mhz normal normal 48 mhz
4 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset serial data interface (smbus) pi6c410m is a slave only smbus device that supports indexed block read and indexed block write protocol using a single 7-bit ad - dress and read/write bit as shown below. data protocol (1) address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 i/0 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit slave addr r/w ack register offset ack byte count = n ack data byte 0 ack data byte n - 1 ack stop bit note: 1 register offset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0. data byte 0: control register bit descriptions type power up condition output(s) affected pin source pin 0 src_0 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_0 17, 18 na 1 src_1 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_1 19, 20 na 2 src_2 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_2 22, 23 na 3 src_3 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_3 24, 25 na 4 src_4 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_4 26, 27 na 5 src_5 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_5 30, 31 na 6 src_6 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled src_6 32, 33 na 7 cpu_2 / src_7 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled cpu_2 / src_7 35, 36 na
5 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset data byte 1: control register bit descriptions type power up condition output(s) affected pin source pin 0 spread spectrum 1 = enable, 0 = disable rw 0 = spread off cpu[0:2], src[0:7], pci[2:5], pcif[0:1] 3, 4, 5, 8, 9, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 56 na 1 cpu_0 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled cpu_0, cpu_0# 43, 44 na 2 cpu_1 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled cpu_1, cpu_1# 40, 41 na 3 reserved rw 4 ref output enable 1 = enabled, 0 = disabled rw 1 = enabled ref 52 na 5 usb_48 output enable 1 = enabled, 0 = disabled rw 1 = enabled usb_48 12 na 6 dot_96 output enable 1 = enabled, 0 = disabled (hi-z) rw 1 = enabled dot_96 & dot96# 14, 15 na 7 pcif_0 output enable 1 = enabled, 0 = disabled rw 1 = enabled pcif_o 8 na data byte 2: control register bit descriptions type power up condition output(s) affected pin source pin 0 pcif_1 output enable 1 = enabled, 0 = disabled rw 1 = enabled pcif_1 9 na 1 reserved rw na 2 reserved rw 3 reserved rw 4 pci _2 output enable 1 = enabled, 0 = disabled rw 1 = enabled pci_2 56 na 5 pci _3 output enable 1 = enabled, 0 = disabled rw 1 = enabled pci_3 3 na 6 pci _4 output enable 1 = enabled, 0 = disabled rw 1 = enabled pci_4 4 na 7 pci _5 output enable 1 = enabled, 0 = disabled rw 1 = enabled pci_5 5 na
6 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset data byte 3: control register bit descriptions type power up condition output(s) affected pin source pin 0 src_0 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_0 17, 18 na 1 src_1 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_1 19, 20 na 2 src_2 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_2 22, 23 na 3 src_3 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_3 24, 25 na 4 src_4 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_4 26, 27 na 5 src_5 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_5 30, 31 na 6 src_6 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_6 32, 33 na 7 src_7 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# src_7 35, 36 na
7 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset data byte 4: control register bit descriptions type power up condition output(s) affected pin source pin 0 cpu_0 output control 0 = free running, 1 = stopped with cpu_stop# rw 1 = stopped with cpu_stop# assertion cpu_0 43, 44 na 1 cpu_1 output control 0 = free running, 1 = stopped with cpu_stop# rw 1 = stopped with cpu_stop# assertion cpu_1 40, 41 na 2 cpu_2 output control 0 = free running, 1 = stopped with cpu_stop# rw 1 = stopped with cpu_stop# assertion cpu_2 35, 36 na 3 pcif_0 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# pcif_0 8 na 4 pcif_1 output control 0 = free running, 1 = stopped with pci_stop# rw 0 = free running, not affected by pci_stop# pcif_1 9 na 5 reserved rw 6 dot_pwrdwn drive mode 1 = hi-z, 0 = driven in pwrdwn rw 0 = driven in power down dot_96 & dot_96# 14, 15 na 7 reserved rw data byte 5: control register bit descriptions type power up condition output(s) affected pin source pin 0 cpu_0 pwrdwn drive mode 1 = hi-z, 0 = driven in pwrdwn rw 0 = driven in power down cpu_0 & cpu_0# 43, 44 na 1 cpu_1 pwrdwn drive mode 1 = hi-z, 0 = driven in pwrdwn rw 0 = driven in power down cpu_1 & cpu_1# 40, 41 na 2 cpu_2 pwrdwn drive mode 1 = hi-z, 0 = driven in pwrdwn rw 0 = driven in power down cpu_2 & cpu_2# 35, 36 na 3 src_pwrdwn drive mode 1 = hi-z, 0 = driven in pwrdwn rw 0 = driven in power down src[0:7] & src[0:7]# 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 35, 36 na 4 cpu_0 stop drive mode 1 = hi-z, 0 = driven in cpu stop rw 0 = driven in cpu_stop cpu_0 & cpu_0# 43, 44 na 5 cpu_1 stop drive mode 1 = hi-z, 0 = driven in cpu stop rw 0 = driven in cpu_stop cpu_1 & cpu_1# 40, 41 na 6 cpu_2 stop drive mode 1 = hi-z, 0 = driven in cpu stop rw 0 = driven in cpu_stop cpu_2 & cpu_2# 35, 36 na 7 src_stop drive mode 1 = hi-z, 0 = driven in pci stop rw 0 = driven in pci_stop src[0:7] & src[0:7]# 17, 18, 19, 20, 22, 23 24, 25, 26, 27, 30, 31 32, 33, 35, 36 na
8 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset data byte 6: control register bit descriptions type power up condition output(s) affected pin source pin 0 fs_a refects the value of the fs_a pin sampled on power up 0 = fs_a was low during vtt_pwrgd# assertion r externally se - lected cpu[0:2] 35, 36, 40, 41, 43, 44 na 1 fs_b refects the value of the fs_b pin sampled on power up 0 = fs_b was low during vtt_pwrgd# assertion r externally se - lected cpu[0:2] 35, 36, 40, 41, 43, 44 na 2 fs_c refects the value of the fs_c pin sampled on power up 0 = fs_c was low during vtt_pwrgd# assertion r externally se - lected cpu[0:2] 35, 36, 40, 41, 43, 44 na 3 pci_stop control 1 = disabled, 0 = enabled, stopped src and pci clocks rw 1 = disabled all pci & src clocks except pcif and src clocks set to free-running 3, 4, 5, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 56 na 4 ref output drive strength 0 = 1x, 1 = 2x rw 1 = 2x ref 52 na 5 reserved rw 6 test clock mode entry control 0 = disabled, 1 = ref/n or hi-z rw 0 = disabled 7 test clock mode 0 = hi-z, 1 = ref/n rw 0 = hi-z cpu[0:2], src[0:7], pci[2:5], pcif[0:1], ref, usb_48, dot_96 3, 4, 5, 8, 9, 12, 14, 15, 17, 18, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 52, 56 na databyte 7: control register bit descriptions type power up condition output(s) affected pin 0 vendor id r 0 na na 1 r 0 na na 2 r 0 na na 3 r 0 na na 4 revision code r 1 na na 5 r 0 na na 6 r 1 na na 7 r 0 na na
9 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset vtt_pwrgd# timing diagram st at e 1 state 0 wa it for vtt_pw rg d# state 2 state 3 0. 2- 0. 3m s dela y on of f fs _a , f s_ b, f s_ c vtt_pw rg d from vr m vtt_pw rg d# vcc cl oc k ge n cl oc k stat e cl oc k ou tp ut s cl oc k vc o on of f vcc co re pw rg ood vt t vcc to vr m 5/ 12v figure 1. cpu power before clock power figure 2. cpu power after clock power stat e 1 stat e 0 wa it for vtt_ p w rg d# stat e 2 stat e 3 0. 2- 0. 3m s dela y o n o ff fs _a , f s_ b, f s_ c vtt_pw rg d from vr m vtt_pw rg d# vc c c lo ck ge n cl oc k s ta te cl oc k ou tp ut s cl oc k v co on o ff vcc co re pw rg ood vt t vc c t o v rm 5/ 12v
1 0 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset clock power-up state machine figure 3. power-up state diagram figure 4. power down sequence power down (pwrdwn assertion) s0 po we r of f s1 dela y >0 .2 5m s s2 samp le i nput str ap s s3 normal op era tio n vtt_pw rg d# = lo w en ab le out pu ts vd da = off vd da = 2 .0 v vtt_pw rg d# = to gg le cpu, 133mhz pwrd wn pci , 33mhz ref cpu#, 133mhz src, 100mhz usb, 48mhz dot#, 96mhz dot, 96mhz src#, 100mhz
1 1 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset power down (pwrdwn de-assertion) figure 5. power down de-assetion figure 6. assertion of cpu_stop# waveforms cpu stop (cpu_stop# assertation) tdrive_pwrdw n <300us, >200mv tstable <1.8m s pci , 33mhz ref dot#, 96mhz dot, 96mhz usb, 48mhz src#, 100mhz src, 100mhz cpu#, 133mhz cpu, 133mhz pwrd wn cpu_stop# cp u cpu#
1 2 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset cpu stop (cpu_stop# de-assertion) figure 7. cpu_stop# de-assertion waveform figure 8. assertion of pci_stop# waveform pci stop (pci_stop# assertion) figure 8. de-assertion of pci_stop# waveform pci stop (pci_stop# de-assertion) tdrive_cpu_stop#, 10ns >200m v cpu_stop# cp u cpu# cpu internal cpu# i nterna l pc if [0:1], 33mhz pc i[ 2:5], 33mhz pc i_stop# src#, 100mhz src, 100mhz su (10ns min.) t t su (10ns mins.) pc i_stop# pc if [0:1], 33mhz pc i[ 2:5], 33mhz src, 100mhz src#, 100mhz tdrive_src < 15ns
1 3 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset src tristate clock truth table signal pwrdwn pci_stop# pci_stop tristate bit pwrdwn tristate bit non-stop stoppable pin pin outputs outputs src[0:7] 0 1 x x running running 0 0 0 x running driven @ iref x 6 0 0 1 x running tristate 1 x x 0 driven @ iref x 2 driven @ iref x 2 1 x x 1 tristate tristate tristate specifcations cpu tristate clock truth table signal pwrdwn cpu_stop# cpu_stop tristate bit pwrdwn tristate bit non-stop stoppable pin pin outputs outputs cpu[0:2] 0 1 x x running running 0 0 0 x running driven @ iref x 6 0 0 1 x running tristate 1 x x 0 driven @ iref x 2 driven @ iref x 2 1 x x 1 tristate tristate cpu clock tristate timing figure 10. cpu_stop = driven, cpu_pwrdwn = driven, dot_pwrdwn = driven dot tristate clock truth table signal pwrdwn pwrdwn tristate bit stoppable pin outputs dot96 0 x running 1 0 driven @ iref x 2 1 1 tristate cp u_ st op # pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee running) cp u (st opp ab le ) cp u# (st op pa bl e) dot dot # 1. 8m s
1 4 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset figure 11. cpu_stop = tristate, cpu_pwrdwn = driven figure 12. cpu_stop = driven, cpu_pwrdwn = tristate figure 13. cpu_stop = tristate, cpu_pwrdwn = tristate, dot_pwrdwn = tristate cp u_ st op # pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee running) cp u (st opp ab le ) cp u# (st op pa bl e) 1. 8m s cp u_ st op # pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee running) cp u (st opp ab le ) pu # (s to pp ab le ) 1. 8m s cp u_ st op # pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee running) cp u (st opp able ) cp u# (st op pa bl e) dot dot # 1. 8m s
1 5 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset figure 14. src_stop = driven, src_pwrdwn = driven figure 15. src_stop = tristate, src_pwrdwn = tristate figure 16. src_stop = tristate, src_pwrdwn = tristate, pci_stop# = asserted pc i_ stop # pc i (f ree ru nn in g) pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee running) src (s to pp ab le ) src# (st oppa bl e) 1. 8m s pc i_ stop # pc i (f ree ru nn in g) pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee runnin g src (s to pp ab le ) src# (st oppa bl e) 1. 8m s 1 pc i cl oc k ma x pc i_ stop # pc i (f ree ru nn in g) pw rd wn cp u (f ree ru nn in g) cp u# ( fr ee running) src (s to pp ab le ) src# (st oppa bl e) 1. 8m s 1 pc i cl oc k ma x
1 6 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset spread spectrum specifcations pi6c410m supports spread spectrum clocking and can be enabled and disabled via smbus control. the maximum spread spec - trum modulation is C0.5% down spread with frequency from 30khz to 33khz. ssc on tperiod ssc off tperiod unit min max min max ns cpu @ 399.000 mhz 2.4993 2.5133 cpu @ 400.000 mhz 2.4993 2.5008 cpu @ 332.500 mhz 2.9991 3.016 cpu @ 333.333 mhz 2.9991 3.0009 cpu @ 266.000 mhz 3.7489 3.77 cpu @ 266.666 mhz 3.7489 3.7511 cpu @ 199.500 mhz 4.9985 5.0266 cpu @ 200.000 mhz 4.9985 5.0015 cpu @ 166.250 mhz 5.9982 6.032 cpu @ 166.666 mhz 5.9982 6.0018 cpu @ 133.000 mhz 7.4978 7.54 cpu @ 133.333 mhz 7.4978 7.5023 cpu @ 99.750 mhz 9.997 10.0533 cpu @ 100.000 mhz 9.997 10.003 src @ 99.750 mhz 9.997 10.0533 src @ 100.000 mhz 9.997 10.003 pcif / pci @ 33.250 mhz 29.991 30.1598 pcif / pci @ 33.333 mhz 29.991 30.009 host clock buffer characteristics min max r o 3000 ? n/a r os unspecifed unspecifed v out n/a 850mv current-mode output buffer characteristics of cpu, src, and dot figure 17. simplifed diagram of a current-mode output buffer ros lout 0.85v slope ~1/r o lout 0v v out = 0.85v max. ro vdd (3.3v 5%)
1 7 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset cueernt accuracy conditions confguration load min. max. i out v dd = 3.30 5% rref = 475 ? nominal test load for given confguration -12% x i nominal +12% x i nominal iref = 2.32ma host clock output current board target trace/term z reference r, iref = v dd /(3xrr) output current voh @ z 100? (100? differential 8% coupling ratio) rref = 475 ? iref = 2.32ma ioh = 6 x iref 0.7v @ 50 crystal recommendations (1) frequency cut loading load cap drive max. shunt cap max. motional cap max. tolerance max. stability max. aging max. 14.31818 mhz at parallel 20pf 0.1mw 5pf 0.016pf 35ppm 30ppm 5ppm note: 1. external trim capacitors (ce) are required. ce = 2*cl C (cs + ci). typical ce = 33pf when crystal-load = 20pf, ctrace (cs) = 2.8pf and c xtal = 4.5pf. absolute maximum ratings (1) (over operating free-air temperature range) symbol parameters min. max. units v dd _a 3.3v core supply voltage -0.5 4.6 v v dd 3.3v i/o supply voltage -0.5 4.6 v ih input high voltage 4.6 v il input low voltage -0.5 ts storage temperature -65 150 c v esd esd protection 2000 v note: 1. stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
1 8 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset dc electrical characteristics (v dd = 3.35%, v dd_a = 3.35%) symbol parameters condition min. max. units vdd_a 3.3v core supply voltage 3.135 3.465 v vdd 3.3v i/o supply voltage 3.135 3.465 v ih 3.3v input high voltage v dd 2.0 v dd + 0.3 v il 3.3v input low voltage v ss C 0.3 0.8 i ik input leakage current 0 < v in < v dd -5 +5 a v ih _fs 3.3v input high voltage 0.7 v dd + 0.3 v v il _fs 3.3v input low voltage v ss C 0.3 0.35 v oh 3.3v output high voltage i oh = -1ma 2.4 v ol 3.3v output low voltage i ol = 1ma 0.4 i oh output high current cpu, src, dot: i oh = 6 x iref, iref = 2.32ma 12.2 ma 15.6 usb v oh = 1.0v -29 v oh = 3.135v -23 ref, pci v oh = 1.0v -33 v oh = 3.135v -33 i ol output low current usb v ol = 1.95v 29 v ol = 0.4v 27 ref, pci v ol = 1.95v 30 v ol = 0.4v 38 cin input pin capacitance 3 5 pf cxtal xtal pin capacitance 3 6 cout output pin capacitance 6 lpin pin inductance 7 nh i dd power supply current v dd = 3.465v, f cpu = 400 mhz 500 ma i ss power down current driven outputs 100 i ss power down current tristate outputs 12 ta ambient temperature 0 70 c
1 9 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset ac electrical characteristics (v dd = 3.35%, v dd_a = 3.35%) symbol outputs parameters min. max. units notes t rise / t fall cpu, src, dot rise and fall time (measured between 0.175v to 0.525v) 175 700 ps 1,2 t rise / t fall pci/pcif, ref rise and fall time (measured between 0.8v to 2.0v) 0.5 2.0 ns 4 t rise / t fall usb rise and fall time (measured between 0.8v to 2.0v) 1.0 2.0 5 t rise / t fall cpu, src, dot rise and fall time variation 125 ps 1, 2 t skew cpu0, cpu1 cpu C cpu skew 100 ps 1,3,6 t skew cpu2 cpu C cpu skew 200 t skew src src C src skew 250 t skew pci/pcif, ref pci C pci skew / ref - ref skew (measured at 1.5v) 500 4 t jitter cpu0, cpu1 cycle C cycle jitter 85 1, 3 t jitter cpu2 cycle C cycle jitter 125 t jitter src cycle C cycle jitter 125 t jitter dot cycle C cycle jitter 250 t jitter pci/pcif cycle C cycle jitter (measured at 1.5v) 500 4 t jitter usb cycle C cycle jitter (measured at 1.5v) 350 5 t jitter ref cycle C cycle jitter (measured at 1.5v) 1000 4 v high cpu, src, dot voltage high including overshoot 660 1150 mv 1, 2 v low cpu, src, dot voltage low including undershoot -300 vcross cpu, src, dot absolute crossing poing voltages 250 550 ? vcross cpu, src, dot total variation of vcross over all edges 140 t dc cpu, src, dot duty-cycle 45 55 % 1,3,6 t dc ref, usb, pci/pcif duty-cycle (measured at 1.5v) 45 55 % 4, 5 t stable all clock stabilization from power-up <1.8 ms fig 2 t drive differential output enable after pwrdwn de-asser - tion 300 s pwrdwn t rise / t fall power down rise and fall time 5.0 ns pwrdwn notes: 1. test confguration is rs = 33.2?, rp = 49.9?, and c l = 2pf. 2. single-ended measurement. 3. differential measurement. 4. pci, pcif, and ref c l (min) = 10pf, c l (max) = 30pf. 5. usb c l (min) = 10pf, c l (max) = 20pf. 6. cpu measured at 133 mhz.
2 0 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset confguration test load board termination figure 18. confguration test load board termination rs = 33? rs = 33? rp = 50? 33? rp = 50 ? 2pf 2pf clock# clock tla tlb pi6c410m note: 1. maximum 10" trace length for cpu @ 200 mhz, 16" trace for src @ 100 mhz.
2 1 ps8736c 12/19/05 pi6c410m/410ma clock generator for intel pci express mobile chipset ordering information (1,2,3) ordering code package code package description pi6c410ma a 56-pin, 240mil wide, 0.5mm pitch tssop pi6c410mae a pb-free & green 56-pin, 240mil wide, 0.5mm pitch tssop pi6c410maae a pb-free & green 56-pin, 240mil wide, 0.5mm pitch tssop PI6C410MAAEX a pb-free & green 56-pin, 240mil wide, 0.5mm pitch tssop , tape and reel notes: 1. thermal characteristics can be found on the company web site at www .pericom.com/packaging/ 2. e = pb-free and green 3. x suffx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com packaging mechcanical: 56-pin, 240mil wide, 0.5mm pitch tssop (a) ???? ???? ??? ?????????? ???? ???? ???? ????? ? ? ?? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??????????????? ?????????????? ???? ???? ???? ???? ???? ???? ???? ??? ??? ???? ???? ???? ???? ???? ???? ????? ???? ???

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